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ADJD-S311-CR999 miniature surface mount rgb digital color sensor data sheet features ? fully integrated rgb+clear digital color sensor ? 10 bit resolution per channel output ? built in oscillator/selectable external clock ? low supply voltage (vdd) 2.5v ? digital i/o via 2-wire serial interface ? adjustable sensitivity for diferent levels of illumination ? low power mode (sleep mode) ? independent gain selection for each channel ? 0c to 70c operating temperature ? industrys smallest form factor C csp 2.2 x 2.2 x 0.76mm ? lead free package description the ADJD-S311-CR999 is a cost efective, 4 channels (rgb+clear) digital output sensor in miniature surface- mount package with a mere size of 2.2 x 2.2 x 0.76mm. it is a cmos ic with integrated rgb flters and analog- to-digital converter front end. this device is designed to cater for wide dynamic range of illumination level and is ideal for applications like portable or mobile devices, which demand higher integration, smaller size and low power consumption. sensitivity control is performed by the serial interface and can be optimized individually for the diferent color channel. the sensor can also be used in conjunction with a white led for refective color man - agement. applications ? general color detection and measurement ? mobile appliances such as mobile phones, pdas, mp3 players,etc. ? consumer appliances ? portable medical equipments ? portable color detector/reader
esd protection diode turn-on during power-up and power-down a particular power-up and power-down sequence must be used to prevent any esd diode from turning on in - advertently. the fgure above describes the sequence. in general, avdd and dvdd should power-up and power- down together to prevent esd diodes from turning on inadvertently. during this period, no voltage should be applied to the ios for the same reason. ground connection agnd and dgnd must both be set to 0v and preferably star-connected to a central power source as shown in the application diagram. a potential diference between agnd and dgnd may cause the esd diodes to turn on inadvertently. electrical specifcations absolute maximum ratings (notes 1 & 2) parameter symbol minimum maximum units notes storage temperature t stg_abs -40 85 c digital supply voltage, dvdd to dvss v ddd_abs .5 3.6 v analog supply voltage, avdd to avss v dda_abs .5 3.6 v input voltage v in_abs .5 3.6 v all i/o pins solder refow peak temperature t l_abs 45 c human body model esd rating esd hbm_abs kv all pins, human body model per jesd -a4-b general specifcations feature value interface 00khz serial interface supply .6v digital (nominal), .6v analog (nominal) powering the device 0v t vdd_ramp v ddd / v dda no voltage must be applied to io's during power-up and power-down ramp time
3 recommended operating conditions parameter symbol minimum typical maximum units free air operating temperature t a 0 5 70 c digital supply voltage, dvdd to dvss v ddd .5 .6 3.6 v analog supply voltage, avdd to avss v dda .5 .6 3.6 v output current load high i oh 3 ma output current load low i ol 3 ma input voltage high level (note 4) v ih 0.7v ddd v ddd v input voltage low level (note 4) v il 0 0.3v ddd v dc electrical specifcations over recommended operating conditions (unless otherwise specifed) parameter symbol conditions minimum typical (note 3) maximum units output voltage high level (note 5) v oh i oh = 3ma v ddd -0.8 v ddd -0.4 v output voltage low level (note 6) v ol i oh = 3ma 0. 0.4 v supply current (note 7) i dd_static (note 8) 3.8 5 ma sleep-mode supply current (note 7) i dd_slp (note 8) ua input leakage current i leak -0 0 ua ac electrical specifcations parameter symbol conditions minimum typical (note 3) maximum units internal clock frequency f _clk_int 6 mhz external clock frequency f _clk_ext 6 40 mhz -wire interface frequency f _ wire 00 khz optical specifcation parameter symbol conditions minimum typical (note 3) maximum units dark ofset v d ee = 0 0 lsb
4 minimum sensitivity (note 3) parameter symbol conditions minimum typical (note 3) maximum units irradiance responsivity re l p = 460 nm, b refer note 9 5 lsb/ (mwcm - ) l p = 54 nm, g refer note 0 78 l p = 645 nm, r refer note 54 l p = 645 nm, clear refer note 64 maximum sensitivity (note 3) parameter symbol conditions minimum typical (note 3) maximum units irradiance responsivity re l p = 460 nm, b refer note 9 3796 lsb/ (mwcm - ) l p = 54 nm, g refer note 0 475 l p = 645 nm, r refer note 688 l p = 645 nm, clear refer note 6590 saturation irradiance for minimum sensitivity (note 12) parameter symbol conditions minimum typical (note 3) maximum units saturation irradiance l p = 460 nm, b refer note 9 6.73 mw/cm l p = 54 nm, g refer note 0 5.74 l p = 645 nm, r refer note 4.03 l p = 645 nm, clear refer note 3.87 saturation irradiance for maximum sensitivity (note 12) parameter symbol conditions minimum typical (note 3) maximum units saturation irradiance l p = 460 nm, b refer note 9 0.7 mw/cm l p = 54 nm, g refer note 0 0. l p = 645 nm, r refer note 0.6 l p = 645 nm, clear refer note 0.6 notes 1. the absolute maximum ratings are those values beyond which damage to the device may occur. the device should not be operated at these limits. the parametric values defned in the electrical specifcations table are not guaranteed at the absolute maximum ratings. the recommended operating conditions table will defne the conditions for actual device operation. 2. unless otherwise specifed, all voltages are referenced to ground. 3. specifed at room temperature (25c) and v ddd = v dda = 2.5v. 4. applies to all di pins. 5. applies to all digital output pins. sdaslv go tri-state when output logic high. minimum v oh depends on the pull-up resistor value.
5 figure 1. typical spectral response when the gains for all the color channels are set at equal. spectral response 0 0.2 0.4 0.6 0.8 1 400 420 440 460 480 500 520 540 560 580 600 620 640 660 680 700 wavelength (nm) relative sensitivity figure 2. serial interface bus timing waveforms sda scl t hd:sta t low t high t su:dat t hd:dat t su:sto t bu f s p s t su:sta t hd:sta sr serial interface timing information parameter symbol minimum maximum units scl clock frequency f scl 0 00 khz (repeated) start condition hold time t hd:sta 4 - s data hold time t hd:dat 0 3.45 s scl clock low period t low 4.7 - s scl clock high period t high 4.0 - s repeated start condition setup time t su:sta 4.7 - s data setup time t su:dat 50 - ns stop condition setup time t su:sto 4.0 - s bus free time between start and stop conditions t buf 4.7 - s notes: (continued) 6 . applies to all digital output and digital input-output pins. 7 . refers to total device current consumption. 8. output and bidirectional pins are not loaded. 9. test condition is blue light of peak wavelength ( l p ) 460 nm and spectral half width ( l ?) 25 nm. 10. test condition is green light of peak wavelength ( l p ) 542 nm and spectral half width ( l ?) 35 nm 11. test condition is red light of peak wavelength ( l p ) 645 nm and spectral half width ( l ?) 20 nm 12. saturation irradiance = (msb)/ (irradiance responsivity)
6 serial interface reference s start condition p stop condition sda scl description the programming interface to the adjd-s311 is a 2-wire serial bus. the bus consists of a serial clock (scl) and a serial data (sda) line. the sda line is bi-directional on adjd-s311 and must be connected through a pull-up resistor to the positive power supply. when the bus is free, both lines are high. the 2-wire serial bus on adjd-s311 requires one device to act as a master while all other devices must be slaves. a master is a device that initiates a data transfer on the bus, generates the clock signal and terminates the data transfer while a device addressed by the master is called a slave. slaves are identifed by unique device addresses. both master and slave can act as a transmitter or a receiver but the master controls the direction for data transfer. a transmitter is a device that sends data to the bus and a receiver is a device that receives data from the bus. the adjd-s311 serial bus interface always operates as a slave transceiver with a data transfer rate of up to 100kbit/s. start/stop condition the master initiates and terminates all serial data transfers. to begin a serial data transfer, the master must send a unique signal to the bus called a start condition. this is defned as a high to low transition on the sda line while scl is high. the master terminates the serial data transfer by sending another unique signal to the bus called a stop condition. this is defned as a low to high transition on the sda line while scl is high. the bus is considered to be busy after a start (s) condition. it will be considered free a certain time after the stop (p) condition. the bus stays busy if a repeated start (sr) is sent instead of a stop condition. the start and repeated start conditions are functionally identical. see fgure 3. figure 3. start/stop condition figure 4. data bit transfer sda scl data valid data change data transfer the master initiates data transfer after a start condition. data is transferred in bits with the master generating one clock pulse for each bit sent. for a data bit to be valid, the sda data line must be stable during the high period of the scl clock line. only during the low period of the scl clock line can the sda data line change state to either high or low.
7 a complete data transfer is 8-bits long or 1-byte. each byte is sent most signifcant bit (msb) frst followed by an ac - knowledge or not acknowledge bit. each data transfer can send an unlimited number of bytes (depending on the data format). figure 6. data bit synchronization figure 5. data byte transfer the scl clock line synchronizes the serial data transmission on the sda data line. it is always generated by the master. the frequency of the scl clock line may vary throughout the transmission as long as it still meets the minimum timing requirements. the master by default drives the sda data line. the slave drives the sda data line only when sending an acknowledge bit after the master writes data to the slave or when the master requests the slave to send data. the sda data line driven by the master may be implemented on the negative edge of the scl clock line. the master may sample data driven by the slave on the positive edge of the scl clock line. figure shows an example of a master implementation and how the scl clock line and sda data line can be synchronized. acknowledge/not acknowledge the receiver must always acknowledge each byte sent in a data transfer. in the case of the slave-receiver and master- transmitter, if the slave-receiver does not send an acknowledge bit, the master-transmitter can either stop the transfer or generate a repeated start to start a new transfer. figure 7. slave-receiver acknowledge scl (master) 8 9 sda (slave-receiver) sda (master-transmitter) lsb acknowledge acknowledge clock pulse sda left high by transmitter sda pulled low by receiver sda scl msb lsb 1 2 8 9 ack 1 2 8 9 no ack s or sr sr or p p sr start or repeated start condition stop or repeated start condition msb lsb sda scl sda data sampled on the positive edge of scl sda data driven on the negative edge of scl
8 in the case of the master-receiver and slave-transmitter, the master generates a not acknowledge to signal the end of the data transfer to the slave-transmitter. the master can then send a stop or repeated start condition to begin a new data transfer. in all cases, the master generates the acknowledge or not acknowledge scl clock pulse. figure 8. master-receiver acknowledge scl (master) 8 9 sda (slave-transmitter) sda (master-receiver) acknowledge clock pulse lsb sda left high by transmitter not acknowledge sda left high by receiver p sr stop or repeated start condition msb lsb r/w a1 a6 a5 a4 a3 a2 a0 slave address 1 1 0 1 1 0 0 addressing each slave device on the serial bus needs to have a unique address. this is the frst byte that is sent by the master-trans - mitter after the start condition. the address is defned as the frst seven bits of the frst byte. the eighth bit or least signifcant bit (lsb) determines the direction of data transfer. a one in the lsb of the frst byte indicates that the master will read data from the addressed slave (master-receiver and slave-transmitter). a zero in this position indicates that the master will write data to the addressed slave (master-transmitter and slave-receiver). a device whose address matches the address sent by the master will respond with an acknowledge for the frst byte and set itself up as a slave-transmitter or slave-receiver depending on the lsb of the frst byte. the slave address on adjd-s311 is 0x74 (7-bits). figure 9. slave addressing
9 a6 a5 a4 a3 a2 a1 a0 w a s a p d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 master sends slave address master writes register address master writes register data master will write data start condition stop condition slave acknowledge a slave acknowledge slave acknowledge data format adjd-s311 uses a register-based programming architecture. each register has a unique address and controls a specifc function inside the chip. to write to a register, the master frst generates a start condition. then it sends the slave address for the device it wants to communicate with. the least signifcant bit (lsb) of the slave address must indicate that the master wants to write to the slave. the addressed device will then acknowledge the master. the master writes the register address it wants to access and waits for the slave to acknowledge. the master then writes the new register data. once the slave acknowledges, the master generates a stop condition to end the data transfer. figure 10. register byte write protocol to read from a register, the master frst generates a start condition. then it sends the slave address for the device it wants to communicate with. the least signifcant bit (lsb) of the slave address must indicate that the master wants to write to the slave. the addressed device will then acknowledge the master. the master writes the register address it wants to access and waits for the slave to acknowledge. the master then generates a repeated start condition and resends the slave address sent previously. the least signifcant bit (lsb) of the slave address must indicate that the master wants to read from the slave. the addressed device will then acknowl - edge the master. the master reads the register data sent by the slave and sends a no acknowledge signal to stop reading. the master then generates a stop condition to end the data transfer. figure 11. register byte read protocol a6 a5 a4 a3 a2 a1 a0 w a s d7 d6 d5 d4 d3 d2 d1 d0 master will write data start condition slave acknowledge a p d7 d6 d5 d4 d3 d2 d1 d0 stop condition a6 a5 a4 a3 a2 a1 a0 r sr master will read data repeated start condition slave acknowledge a master not acknowledge a slave acknowledge master sends slave address master writes register address master sends slave address master reads register data
0 application diagram star co nne ct ed gr ou nd reset sdasl v scksl v sl ee p 10 k 10 k 10 k 10 k dv dd re se t sd as lv sc ks lv cl k_ io ho st sy st em ho st sy st em volt age re gul at or volt age re gul at or av dd a gn d dg nd d vd d high level description the sensor needs to be confgured before it can be used. the gain selection needs to be set for optimum perfor - mance depending on light levels. the fowcharts below describe the diferent procedures required. sensor gain optimization fowchart figure 12. typical application diagram sensor operation fowchart * please refer to application note for more detailed information. hardware reset select sensor gain setting acquire and trim offset sensor operation stop acquire sensor reading hardware reset select sensor gain setting acquire sensor output sensor output optimum? sensor gain optimization stop no yes
detail description a hardware reset (by asserting xrst) should be performed before starting any operation. sensor gain settings the sensor gain can be adjusted by varying the number of capacitors and integration time slot of the sensor manually through the following registers. address (hex) register description 6 cap_red number of red channel capacitors 7 cap_green number of green channel capacitors 8 cap_blue number of blue channel capacitors 9 cap_clear number of clear channel capacitors a int_red number of red channel integration time slots c int_green number of green channel integration time slots e int_blue number of blue channel integration time slots 0 int_clear number of clear channel integration time slots sensor adc output registers to obtain sensor adc value, 01 hex must be written to ctrl register. then, read the value from ctrl register. if value is 00h, can read sensor output from data register. address (hex) register description 00 ctrl control register 40 data_red_lo red channel adc data C low byte 4 data_red_hi red channel adc data C high byte 4 data_green_lo green channel adc data C low byte 43 data_green_hi green channel adc data C high byte 44 data_blue_lo blue channel adc data C low byte 45 data_blue_hi blue channel adc data C high byte 46 data_clear_lo clear channel adc data C low byte 47 data_clear_hi clear channel adc data C high byte * please refer to application note for more detailed information. setup value for number of integration time slot the following value can be written to each of the integra - tion time registers to adjust the gain of the sensor. the default value after reset for these registers is 00h. these registers control the number of integration time selected for each channel. the integration time slot can be varied from 00h to fffh. more integration time slot will give higher sensitivity. setup value for number of capacitor the following value can be written to each of the capacitor registers to adjust the gain of the sensor. the default value after reset for these registers is 0fh. these registers control the number of capacitors selected for each channel. the maximum selectable capacitor is 16 with the registers starting from 0 (i.e. 0 to 15). less capacitor will give higher sensitivity. value (hex) number of capacitor 00 0 0 3 03 4 04 5 05 6 06 7 07 8 08 9 09 0 0a 0b 0c 3 0d 4 0e 5 0f 6 * please refer to application note for more detailed information.
mechanical drawing pin information pin name type description a dvdd power digital power pin a sckslv input serial interface clock pin a3 avdd power analog power pin b clkio input external clock input b sdaslv input/output bidirectional data pin. a pull-up resistor should be tied to sdaslv because it goes tri-state to output logic b3 sleep input when sleep = , the device goes into sleep mode. in sleep mode, all analog circuits are powered down and the clock signal is gated away from the core logic resulting in very low current consumption. c dgnd ground tie to digital ground c reset input global, asynchronous, active-low system reset. when asserted low, xrst resets all registers. minimum reset pulse low is us and must be provided by external circuitry. c3 agnd power tie to analog ground dimensions description nominal (um) package body dimension x 00 package body dimension y 00 package height 760 ball diameter 50 total pin count 9 note: 1. dimensions are in milimeters (mm) 2. standard tolerances (unless otherwise specifed) a. linear tolerance = +/-0.1mm b. angular tolerance = +/-1 pin confguration 3 a dvdd sckslv avdd b clkio sdaslv sleep c dgnd reset agnd
3 recommended underfll type and characteristic ? henkel fp4548 ? low moisture absorption ? low cte ? underfll up to 70-85% of height nsmd nsmd 310 um 560 um 310 um 560 um recommended pcb land pad design ? niau fash over copper pad ? pad diameter (c)= 0.20 mm ? nsmd diameter (d)= 0.25 ~ 0.30 mm recommended stencil design ? stencil thickness 5 mils ? stencil type ni electroforming ? stencil aperture type square ? stencil aperture 310 um ? additional feature rounded square edge after soldering or mounting precaution please ensure that all soldered or refowed csp package that is mounted on the pcb is not exposed to compres - sion or loading force directly perpendicular to the fat top surface. precaution: excessive loading force directly perpendicular to the fat top surface may cause pre-mature failure. height 70 ~ 85% underfill pcb height 70 ~ 85% underfill pcb pcb loading force
4 delta-flux max. 2 c/sec. t- m in. t- m ax. t -reflow t -peak t-reflow t-pre 100 ~ 140 sec. 90 ~ 120 sec. 160 c 180 c 217~220 c 240 5 c time tempera ture delta-cooling max. 2 c/sec. delta-ramp max. 2 c/sec. t-com p recommendations for handling and storage of ADJD-S311-CR999 this product is qualifed as moisture sensitive level 3 per jedec j-std-020. precautions when handling this moisture sensitive product is important to ensure the reliability of the product. do refer to avago application note an5305 handling of moisture sensitive surface mount devices for details. a. storage before use ? unopened moisture barrier bag (mbb) can be stored at 30c and 90%rh or less for maximum 1 year ? it is not recommended to open the mbb prior to assembly (e.g. for iqc) ? it should also be sealed with a moisture absorbent material (silica gel) and an indicator card (cobalt chloride) to indicate the moisture within the bag b. control after opening the mbb ? the humidity indicator card (hic) shall be read immediately upon opening of mbb ? the components must be kept at <30c/60%rh at all time and all high temperature related process including soldering, curing or rework need to be completed within 168hrs c. control for unfnished reel ? for any unused components, they need to be stored in sealed mbb with desiccant or desiccator at <5%rh d. control of assembled boards ? if the pcb soldered with the components is to be subjected to other high temperature processes, the pcb need to be stored in sealed mbb with desiccant or desiccator at <5%rh to ensure no components have exceeded their foor life of 168hrs e. baking is required if: ? 10% or 15% hic indicator turns pink ? the components are exposed to condition of >30c/60%rh at any time. ? the components foor life exceeded 168hrs ? recommended baking condition (in component form): 125c for 24hrs recommended refow profle it is recommended that henkel pb-free solder paste lf310 be used for soldering ADJD-S311-CR999. below is the rec - ommended refow profle.
5 package tape and reel dimensions reel dimensions carrier tape dimensions ? 1.50 + 0.10 - 0.0 0 ? 1.50 min (p1)8.00 0.10 (p0)4.00 0.10 (p2)2.00 0.10 r0.50 (a0)2.60 0.10 (e1)1.75 0.10 (f)5.50 0.05 (t)0.30 0.05 (k0)0.90 0.10 (b0)2.60 0.10 (w)12.00 0.10 notes: 1. ao and bo measured at 0.3mm above base of pocket 2. 10 pitches cumulative tolerance is 0.2mm 3. dimensions are in millimeters (mm) notes: 1. *measure at hub area. 2. all fange edges to be rounded. 18.0 max.* 178.0 0.5 12.4 45 45 65 r10.65 r5.2 +1.5* - 0.0 55.0 0.5 176.0 512 embossed ribs raised: 0.25 mm width: 1.25 mm back view
6 appendix a: sensor register list add (dec) add (hex) mnemonic width reset (dec) type access b7 b6 b5 b4 b3 b2 b1 b0 notes 0 0 ctrl 2 0 bits r/ w gofs gss r 1 1 config 3 0 bits r/ w extclk slee p t of s 6 6 cap_re d 4 15 number r/w 7 7 cap_green 4 1 5 n umbe r r /w 8 8 cap_blue 4 1 5 n umbe r r /w 9 9 cap_clea r 4 15 number r/w 10 a i nt_r ed _l o 8 0 n umbe r r /w 11 b i nt_r ed _h i 8 0 n umbe r r /w 12 c i nt_green_l o 8 0 n umbe r r /w 13 d i nt_green_h i 8 0 n umbe r r /w 14 e i nt_blue_lo 8 0 number r/w 15 f int_blue_h i 8 0 n umber r/w 16 10 int_clear_l o 8 0 n umbe r r /w 17 11 int_clear_hi 8 0 numbe r r /w 64 40 data_r ed _lo 8 0 numbe r r 65 41 data_r ed _h i 3 0 n umbe r r 66 42 data_gree n_lo 8 0 number r 67 43 data_gree n_hi 3 0 number r 68 44 data_blu e_ lo 8 0 number r 69 45 data_blu e_ hi 3 0 number r 70 46 data_clea r_lo 8 0 number r 71 47 data_clea r_hi 3 0 number r 72 48 offse t_ re d 8 0 n umbe r r sign _red 73 49 offse t_ gree n 8 0 n umbe r r sign_green 74 4a offse t _blue 8 0 number r sign_blu e 75 4b offset_clea r 8 0 n umbe r r sign_clea r n/a data_red[9:8] data_gree n[9:8] data_blue[9:8] data_clear[9:8] n/a n/a n/a int_green[7:0] cap_red[3:0] cap_green[3:0] cap_blue[3:0 ] f n int_clear [1 1:8] n/a int_red[7:0] int_red[11:8] int_green[11:8 ] int_blue[7:0 ] in t_blue[11:8] n/a 11/10-bit data int_clear[7:0] n/a n/a sign = 1 is - ve offset data offse t_red[6:0] offset_green[6:0] offset_blue[6:0] offset_clear[ 6: 0] se nso r sample data data_red[7:0] da ta_green [7 :0 ] data_blu e[7:0 ] data_clear[7:0] n/a n/ a c ap_clear[3:0]
7 appendix a: sensor register list 1) ctrl: control register b7 b6 b5 b4 b3 b2 b1 b0 gofs gssr n/a gssr gofs n/a get offset reading. active high and automatically cleared. result is stored in registers 72-75 (dec) get sensor reading. active high and automatically cleared. result is stored in registers 64-71 (dec) not available. 2) config: confguration register 3) cap_red: capacitor settings register for red channel 4) cap_green: capacitor settings register for green channel 5) cap_blue: capacitor settings register for blue channel 6) cap_clear: capacitor settings register for clear channel b7 b6 b5 b4 b3 b2 b1 b0 extclk sleep tofs n/ a extclk sleep tofs n/ a trim offset mode. active high. not available. external clock mode. active high. sleep mode. active high and external clock mode only. automatically cleared if otherwise. b7 b6 b5 b4 b3 b2 b1 b0 n/a cap_red n/a cap_red[3:0] not available. number of red channel capacitors. b7 b6 b5 b4 b3 b2 b1 b0 n/a cap_green n/a cap_green[3:0] not available. number of green channel capacitors. b7 b6 b5 b4 b3 b2 b1 b0 n/a cap_blue n/a cap_blue[3:0] not available. number of blue channel capacitors. b7 b6 b5 b4 b3 b2 b1 b0 n/a cap_clear not available. number of clear channel capacitors. n/a cap_clear[3:0]
8 7) int_red: integration time slot setting register for red channel 8) int_green: integration time slot setting register for green channel 9) int_blue: integration time slot setting register for blue channel 10) int_clear: integration time slot setting register for clear channel 11) data_red_lo: low byte register of red channel sensor adc reading b7 b6 b5 b4 b3 b2 b1 b0 data_red[7:0] data_red red channel adc data. b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 int_re d n umber of red channel integration time slots. int_red[11:8] n/a int_red[7:0] b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 int_green number of green channel integration time slots. in t_ gr een[11:8 ] n/a int_green[7:0] b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 int_blue number of blue channel integration time slots. int_blue[11:8] n/ a int_blue[7:0 ] b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 int_clear number of clear channel integration time slots. in t_clear[11:8 ] n/a int_clear[7:0 ]
9 14) data_green_hi: high byte register of green channel sensor adc reading 15) data_blue_lo: low byte register of blue channel sensor adc reading 16) data_blue_hi: high byte register of blue channel sensor adc reading 17) data_clear_lo: low byte register of clear channel sensor adc reading 18) data_clear_hi: high byte register of clear channel sensor adc reading b7 b6 b5 b4 b3 b2 b1 b0 data_blue[7:0] data_blue blue channel adc data. b7 b6 b5 b4 b3 b2 b1 b0 data_clear[7:0] data_clear clear channel adc data. b7 b6 b5 b4 b3 b2 b1 b0 data_green[7:0] data_green green channel adc data. 12) data_red_hi: high byte register of red channel sensor adc reading 13) data_green_lo: low byte register of green channel sensor adc reading b7 b6 b5 b4 b3 b2 b1 b0 n/a data_red[9:8] n/ a data_red not a va il abl e. red channel adc data . b7 b6 b5 b4 b3 b2 b1 b0 n/a data_green[9:8] n/ a data_green not a va il abl e . gr een channel adc data. b7 b6 b5 b4 b3 b2 b1 b0 n/ a d ata_blue[9:8] n/ a data_blue not a va il abl e . blue c hannel adc da ta . b7 b6 b5 b4 b3 b2 b1 b0 n/a data_clear[9:8 ] n/ a data_clear not a va il ab le . clear c hannel adc data .
21) offset_blue: ofset data register for blue channel 22) offset_clear: ofset data register for clear channel b7 b6 b5 b4 b3 b2 b1 b0 sign_blue offset_blue[6:0] sign_blue offset_blue sign bit. 0 = positive, 1 = negative. blue channel adc offset data. b7 b6 b5 b4 b3 b2 b1 b0 sign_clear offset_clear[6:0] sign_clear offset_clear sign bit. 0 = positive, 1 = negative. clear channel adc offset data. 19) offset_red: ofset data register for red channel 20) offset_green: ofset data register for green channel b7 b6 b5 b4 b3 b2 b1 b0 sign_red offset_red[6:0] sign_red offset_red sign bit. 0 = positive, 1 = negative. red channel adc offset data. b7 b6 b5 b4 b3 b2 b1 b0 sign_green offset_green[6:0] sign_green offset_green sign bit. 0 = positive, 1 = negative. green channel adc offset data. for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies, limited in the united states and other countries. data subject to change. copyright ? 007 avago technologies limited. all rights reserved. av0 -09 en - july 30, 007

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